- Lead full-chip physical verification and drive DRC/LVS signoff for complex SoC designs
- Develop custom design-specific checks and advanced verification methodologies
- Perform multi-patterning verification and optimization for advanced technology nodes
- Implement advanced fill strategies to meet density requirements while minimizing design impact
- Interface with foundry to resolve design rule clarifications and obtain waiver approvals
- Mentor verification engineers on debugging techniques and verification best practices
- Develop verification automation and flow improvements to enhance productivity
- Conduct verification correlation studies and drive signoff quality improvements