PQAngels Technologies is looking for experienced Design Verification Engineers to work on challenging ASIC, SoC, and Subsystem verification projects.
We are looking for engineers with strong hands-on expertise in SystemVerilog and UVM, along with experience verifying complex designs and high-speed interfaces.
What You Will Work On
- Develop and enhance SystemVerilog/UVM-based verification environments
- Create verification plans, test strategies, test scenarios and test cases
- Perform functional verification at IP, Subsystem and SoC levels
- Develop reusable UVM components and verification infrastructure
- Implement SystemVerilog Assertions (SVA)
- Analyze functional coverage and drive coverage closure
- Execute simulations, regressions and debug failures
- Perform RTL/ testbench debugging and root-cause analysis
- Verify high-speed protocols and interfaces
- Support verification signoff and project closure
- Work closely with RTL, Architecture, Integration and other engineering teams
- Participate in technical reviews and customer discussions when required
Requirements
Must-Have Skills
- 5-11 years of relevant Design Verification experience
- Strong hands-on SystemVerilog
- Strong hands-on UVM
- Experience with Functional Coverage
- Good experience in SVA
- ASIC / SoC / Subsystem / IP verification experience
- Strong debugging and root-cause analysis skills
- Experience with one or more high-speed interfaces:
- PCIe
- DDR / DDR4 / DDR5 / LPDDR
- USB
- Ethernet
- NoC
- Scripting knowledge in Python / Perl / TCL
- Good understanding of ASIC/VLSI verification methodology and flow
Education: B.E./B.Tech/M.E./M.Tech in ECE, Electrical, Electronics, VLSI, Microelectronics or related fields.
Benefits
Why PQAngels?
- Work on advanced Semiconductor / ASIC / VLSI projects
- Exposure to IP, Subsystem and SoC verification
- Chance to work with experienced semiconductor engineers
- Exposure to global projects and customers
- Strong technical learning and career-growth opportunities