Lead GLS Verification Engineer

Location: Bengaluru

Experience: 8–12 Years

Role Overview:

We are looking for a Lead GLS Verification Engineer with solid expertise in Gate-Level Simulation, SystemVerilog and UVM to drive verification and sign-off of complex SoC designs.

Key Responsibilities
Lead Gate-Level Simulation (GLS) and post-synthesis/post-layout verification activities.
Develop and debug SystemVerilog/UVM-based testbenches and test scenarios .
Validate synthesized netlists across functional, timing and power-aware scenarios .
Analyze GLS failures and debug issues across RTL, netlist, SDF and timing constraints .
Execute SDF-annotated simulations for setup/hold and timing validation.
Develop test strategies for X-propagation, reset, clocking and initialization issues.
Collaborate with RTL, Design, DFT, STA, Synthesis and Physical Design teams for issue resolution.
Drive regression,



coverage analysis and verification sign-off .
Develop automation using Python/Perl/Tcl to improve GLS flows and debug efficiency.

Required Skills
8–12 years of ASIC/SoC verification experience.
Robust hands-on expertise in SystemVerilog and UVM .
Strong experience in Gate-Level Simulation and SDF annotation .
Good understanding of RTL-to-netlist flow, synthesis, STA and timing concepts .
Experience with X-propagation, reset/clock-domain issues and GLS debug .
Strong debugging skills with simulation tools such as VCS/Verdi or equivalent .
Positive scripting/programming skills in Python, Perl or Tcl .
Experience working on complex SoC/IP verification and tape-out activities .

📌 Lead Gls Verification Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru