Req ID 10790937
Job Title: Engineer
Work Location: ~~HYDERABAD~
Skills Required: EIS : ASIC Frontend - Modeling, RTL design and Implementation
Experience: 4-6
Role Descriptions: FPGA RTL Designer Solid experience in RTL design using Verilog/System Verilog. Solid understanding of digital design fundamentals and computer architecture. Experience with FPGA development flows from RTL to bitstream generation.
Essential Skills: FPGA RTL Designer Strong experience in RTL design using Verilog/System Verilog. Solid understanding of digital design fundamentals and computer architecture. Experience with FPGA development flows from RTL to bitstream generation.
Desirable Skills:
Keyword:
Skills: EIS : ASIC Frontend - Modeling| RTL design and Implementation
Experience Required: 4-6
📌 96091-1 - Frontend RTL design (India)
🏢 Objectwin Technology India
📍 India
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