? We’re Hiring | STA Engineer | 5+ Years
LeadSoc Technologies Pvt. Ltd. is looking for experienced Static Timing Analysis (STA) Engineers to join our VLSI team in Bangalore.
? Position: STA Engineer
? Experience: 5+ Years
? Location: Bangalore
? Notice Period: 0–Immediate Joiners Preferred
? Key Responsibilities
- Perform block-level and full-chip Static Timing Analysis (STA)
- Analyze and resolve setup and hold timing violations
- Develop, validate, and debug SDC timing constraints
- Perform MMMC/PVT timing analysis and closure
- Work on clock and timing-path analysis
- Support timing ECOs and optimization
- Collaborate with Physical Design, Synthesis, and Signoff teams
- Debug complex timing issues and drive timing closure
- Support timing signoff activities
?️ Required Skills
- Robust hands-on experience in STA and Timing Closure
- Good knowledge of SDC constraints
- Expertise in Setup/Hold analysis
- Experience with PrimeTime / Tempus
- Knowledge of MMMC, PVT, OCV/AOCV/POCV
- Understanding of CTS, clock analysis, and Physical Design flow
- Scripting knowledge in Tcl / Perl / Python is an advantage
- Experience with ECO implementation and timing optimization
? Education
- B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering (ECE), Electrical Engineering (EEE), VLSI, or a related field
- Strong academic background with relevant VLSI/ASIC design knowledge preferred.
? Preferred Profile
Candidates with solid experience in full-chip/block-level STA, timing debug, constraint development, and signoff closure are preferred.
? Interested candidates can share their updated resume at:
[email protected]
📌 STA Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru