Responsibilities

- 5 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM.
- Strong knowledge of UVM, advance UVM, System Verilog.
- Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM.
- Understanding of complete functional verification cycle will be added advantage.
- Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required.
- Skills to debug RTL & testbench issues, test failures.
- Experience on verification closure by closing Coverage and bug reports.
- Primarily knowledge of Script development and maintenance.
- Understanding of customer dynamic workplace change and adopt run time changes in schedule,



design etc.
- MUST Be willing to Lead a Team of min 4-5 Engineers.
- Must be willing to work from Hyderabad office or customer location as per project demands.

Qualifications

- B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

Required Skills

- Strong knowledge of UVM, advance UVM, System Verilog.
- Skills to debug RTL & testbench issues, test failures.

Preferred Skills

- Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar.

📌 Senior Design Verification Engineer (Bengaluru)
🏢 eInfochips (An Arrow
📍 Bengaluru