Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes.
Must-Have - Hands on experience on Full chip floor plan, Full chip PNR, Design Partitioning
Hands on experience on IO Planning, Bump Plan and RDL Routing
Experience on ECOs, Synthesis and STA, Power analysis
Hands on experience on Physical verification
Hands on experience on 7nm and 10nm technology nodes
Good-to-Have Effective communication skills to interact with cross functional teams.