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MTS Full chip STA (FCT) SILICON DESIGN ENGINEER

THE ROLE:
• As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. You will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.

KEY RESPONSIBILITIES:
• Owns Full chip Timing Closure
• Drive recent improvement in closure




• Analysis of data and feedback to PD execution team
• SDC analysis and feedback
• Work with PnR engineer for timing convergence
• Drive the common STA methodology in the business unit
• Work and collaborate with different business units, CAD and central methodology team to drive the requirement
• Automation to refine and improve design signoff requirement and dashboarding
• Ability to organize and present complex technical information in a crisp and concise manner.
• Interact with other PPA (equivalent) teams internal to AMD
• Identify best practices across AMD and industry to update and improve flow/project settings
• To increase the competitiveness of each stage in AMD design flow
• Ability to work with multi-level functional teams across various geographies.
• Highly organized, strong affinity for automation and prioritization.

PREFERRED EXPERIENCE:
• Timing closure experience at

📌 Full Chip Timing Lead (Hyderabad)
🏢 Advanced Micro Devices
📍 Hyderabad