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Physical Design Lead with STA:

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THE ROLE:
• Specialized in Clock build , clock push down from top to block, guide tile for latency and skew
• As a member of the PD pnr team responsible for owning and leading SubSystem of 10 or more partitions. SoC SS PD closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for RTL to GDS execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.

THE PERSON:




• A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.
• Strong self-driving ability, should have excellent communication skills (both written and oral)

KEY RESPONSIBILITIES:
• Owns SS Partitions PnR execution and closure
• Drive current improvement in closure
• Analysis of data and feedback to Design team
• Work with PnR team members for closure convergence starting from Synthesis to Route
• Closure signoff on STA, EMIR, PV
• Work and collaborate with different business units, CAD and central methodology team to drive the requirement
• Automation to refine and improve design signoff requirement and dashboarding
• Ability to organize and present complex technical information in a crisp and concise manner.
• Interact with other PPA (equiv

📌 Physical Design Lead with STA (Hyderabad)
🏢 Advanced Micro Devices
📍 Hyderabad