Work Mode: Full-time | On-site / Hybrid
Experience: 6+ Years
Role Overview
We are looking for a Senior Verification Engineer with experience in SoC-level verification of high-speed interface IP. The role involves verification environment development, test porting, regression execution, debug across RTL/GLS/timing simulations, and support for silicon bring-up. Experience with high-speed interfaces and third-party VIP integration is required.
Key Responsibilities
- Develop and execute SoC-level verification for high-speed interface IP.
- Develop and maintain verification environments using System Verilog and UVM/OVM.
- Implement constrained random verification and functional verification strategies.
- Perform test porting from IP/subsystem environments to SoC-level environments.
- Support SoC-level integration of high-speed interface IP.
- Bring up and debug verification testbenches and regressions.
- Integrate and validate third-party VIP within SoC verification environments.
- Debug failures across RTL simulation, GLS and timing simulation.
- Develop, execute and analyze simulation regressions and coverage.
- Support silicon bring-up, post-silicon debug and validation activities.
- Develop and execute loopback tests and interface-specific verification scenarios.
- Work with design, architecture, validation and integration teams to resolve verification issues.
Required Qualifications
- 6+ years of experience in ASIC/SoC verification.
- Solid hands-on experience with System Verilog.
- Strong experience with UVM/OVM methodology.
- Experience in SoC-level integration and verification.
- Practical experience in test porting and regression execution.
- Experience debugging RTL, GLS and timing simulations.
- Experience with verification testbench bring-up and VIP integration.
- Understanding of at least one or more high-speed interfaces such as USB, PCIe, UFS, MIPI or DDR.
- Experience with loopback testing is preferred.
Technical Skills Verification
- System Verilog
- UVM / OVM
- Constrained Random Verification
- Functional Verification
- Testbench Development
- Regression Testing
- Coverage Analysis
SoC Integration & Debug
- SoC-Level Verification
- SoC-Level Integration
- Test Porting
- Testbench Bring-up
- Third-Party VIP Integration
- RTL Simulation
- Gate-Level Simulation (GLS)
- Timing Simulation
- Simulation Debug
High-Speed Interfaces
- USB
- PCIe
- UFS
- MIPI
- DDR
- Loopback Tests
Scripting
- Python
- Perl
- Tcl
📌 Senior Verification Engineer – High-Speed IO (SoC) (India)
🏢 Best NanoTech
📍 India
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