Senior Verification Engineer DDR PHY Location

Bangalore, India

Work Mode

On-site / Hybrid, depending on project requirements

Experience

6+ years

Role Overview

We are looking for a Senior Verification Engineer with hands-on experience in DDR PHY verification and memory interface technologies. The role involves verification ownership from test plan development through regression, debug, vector delivery, and quality sign-off. Strong knowledge of DDR PHY architecture, DFI protocol, JEDEC standards, and LPDDR4/LPDDR5 is required.

Key Responsibilities

- Own DDR PHY verification activities from verification planning and test plan development through final quality sign-off.

- Develop and execute verification plans for DDR PHY and memory interface functionality.

- Develop, maintain, and debug System Verilog/UVM-based verification environments and testbenches.

- Verify DDR PHY functionality against applicable JEDEC specifications and interface requirements.

- Develop and execute functional, protocol, corner-case, and negative test scenarios.

- Work with DFI protocol interfaces and verify PHY/controller interactions.

- Develop and maintain simulation regressions, analyze failures, and drive issues to closure.

- Debug RTL, testbench, simulation, and system-level failures using waveform and log analysis.

- Investigate root causes across SS/SoC integration and post-silicon issues.

- Support vector development, validation, coverage analysis, and verification quality sign-off.

- Collaborate with RTL, architecture, design,



physical design, firmware, and post-silicon teams.

- Document verification results, debug findings, coverage status, and sign-off metrics.

Required Qualifications
- 6+ years of relevant experience in ASIC/SoC verification.

- Hands-on experience in DDR PHY verification.

- Solid understanding of DDR PHY architecture and memory interface operation.

- Hands-on experience with LPDDR5 and/or LPDDR4.

- Strong knowledge of DFI protocol.

- Working knowledge of relevant JEDEC DDR/LPDDR standards and recent generations.

- Strong programming and verification experience using Verilog/System Verilog.

- Hands-on experience with UVM and/or OVM.

- Strong simulation, regression, waveform, and functional debug skills.

- Experience in root-cause analysis of complex RTL/SoC verification issues.

Technical Skills DDR / Memory Interfaces
- DDR PHY Architecture

- LPDDR5

- LPDDR4

- DFI Protocol

- JEDEC Standards

- Memory Controller / PHY Interface

Verification
- Verilog

- System Verilog

- UVM

- OVM

- Verification Planning

- Test Plan Development

- Testbench Development

- Functional Verification

- Regression

- Coverage Analysis

- Vector Development

Debug
- RTL Debug

- Simulation Debug

- Waveform Analysis

- Regression Failure Debug

- Root Cause Analysis

- SoC-Level Debug

- SS / Silicon-Level Issue Debug

System / Integration
- SoC Integration

- Post-Silicon Debug

- Hardware-Software Debug

- AHB / AXI Protocols

Scripting
- Perl scripting

📌 Senior Verification Engineer – DDR PHY (India)
🏢 Best NanoTech
📍 India