**Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing creative ASIC solutions for Facebook's data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer, Formal Verification Responsibilities: 1. Propose, implement and promote the Formal Verification Methodology to be used across the group, both at the top level and at the block level 2. Work with Architecture and Design teams to come up with Formal Verification specification and implementation 3. Define Formal Verification scope, create Formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level 4. Build reusable/scalable environments for Formal Verification and deploying tools 5.



Evaluate and recommend EDA solutions for Formal Verification **Minimum Qualifications:** Minimum Qualifications: 6. Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience 7. 2+ years of experience in formal verification 8. Experience with Formal Verification applications including datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc 9. Experience with formal verification methodologies, complexity reduction techniques, and abstraction techniques 10. Experience partnering with architecture, design, and validation teams to define formal verification scope and drive sign-off 11. Fluency in hardware description languages, such as SystemVerilog and SVA 12. Proficiency in scripting languages such as Python, Perl, or Tcl 13. Experience with JasperGold or VC-Formal **Preferred Qualifications:** Preferred Qualifications: 14. Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators 15. Experience with simulators and waveform debugging tools 16. Experience interpreting hardware specifications and extracting design behaviors and properties for formal verification 17. Experience with complex SoCs 18. Experience with development of fully automated flows from specification to fully verified designs 19. Formal verification experience in clock domain crossing, IP-XACT based register verification and low power **Industry:** Internet

📌 ASIC Engineer, Formal Verification (Bengaluru)
🏢 Meta
📍 Bengaluru