Experience: 4+ Years
Location: Hyderabad / Bangalore
Positions: Senior / Lead
Required Skills :
He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimisation, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs schematic (LVS) checks, and antenna checks. He/She should have worked on 65nm or lower node designs with advanced low-power techniques such as Voltage Islands, Power Gating and substrate bias.
• Provide technical guidance and mentoring to physical design engineers.
• Interface with front-end ASIC teams to resolve issues.
• Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
• Timing closure on DDR2/DDR3/PCIE interfaces.
• Excellent communication skills.
• Strong background in ASIC Physical Design: Floor planning, P&R;, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime-SI.
• Valuable written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritise work based on project needs.