CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is easy: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.
We are seeking a Senior Design Verification Engineer (5–7 years of experience) to join our Data Center Connectivity DV team. This role is ideal for engineers passionate about building verification environments from the ground up, performing functional and power-aware simulations,
and integrating VIPs for standard protocols such as MAC, PHY, and AXI. The position involves CPUSS integration, verification of cutting-edge technologies.
Key Responsibilities
• Take ownership oftest-bench development usingUVM for Subsystem and SoC.
• Translate test bench architecture specifications into detailed DV tasks and build verification environments from scratch.
• Develop key test bench components including agents, scoreboards for data integrity checks, pass/fail criteria, protocol assertions, and functional coverage points
• Set up UVM register model generation using register description files and industry-standard automation tools (e.g.,Autogen).
• Automate C-based register programming API generation from register description files through scripting.
• Perform complete address map and register verification using UVM Register methodology.
• Verify all features com