Experience: 6–15 Years
Locations: Chennai | Bangalore | Hyderabad
Department: Semiconductor / ASIC / SoC Engineering
? About the Role
HCLTech is looking for a highly accomplished Design Verification Engineer (DV) to lead verification for our most critical ASIC and SoC programs. This is a senior technical leadership role that demands deep expertise in verification methodologies and a proven ability to drive large‑scale verification projects from strategy to sign‑off.
If you are passionate about building next‑generation silicon with world‑class quality, this chance is for you.
? Key Responsibilities
• Lead and define end‑to‑end verification strategy for complex ASIC/SoC programs
• Architect and develop robust UVM-based verification environments and testbenches
• Leverage advanced verification methodologies—UVM, Formal Verification, Assertions
• Work hands‑on with industry-leading tools (simulators, formal tools, debuggers)
• Debug complex failures, perform root-cause analysis, and partner with design teams
• Drive code quality, enforce best practices,
and participate in design/code reviews
• Mentor and guide junior DV engineers; foster a high‑performance technical culture
• Stay ahead of emerging verification technologies, tools, and methodologies
• Influence the verification roadmap and contribute to technical decision-making
? Qualifications
• Master’s (preferred) or Bachelor’s degree in Electrical/Computer Engineering
• 6+ years of experience in Design Verification for complex ASIC/SoC designs
• Hands‑on expertise with UVM, SystemVerilog, Verilog/VHDL, Assertions
• Deep understanding of digital design fundamentals
• Strong experience with simulators, formal verification tools, and scripting (Perl/Python/Tcl)
• Proven track record of leading verification teams and driving project success
• Excellent communication, leadership, analytical, and troubleshooting skills
• Ability to handle multiple priorities and deliver under aggressive timelines