CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is straightforward: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

We are looking for an RTL Design Engineer (5–7 years’ experience) to join our Data Center Connectivity design team. This role is ideal for engineers passionate about RTL, microarchitecture, interconnect logic, and front-end design flows driving high-bandwidth,



low-latency systems.

Key Responsibilities

• Take ownership of RTL design and microarchitecture for IP/Subsystems.
• Work from high-level architectural specs and break them down into detailed microarchitecture and build synthesizable RTL from scratch.
• Design efficient Datapath and control logic — think queues, arbiters, FIFOs, and clock-domain crossings — that can scale for high bandwidth and low latency.
• Collaborate closely with architects, and SoC level cross functional teams to make sure the design meets performance, power, and area goals.
• Write clear and maintainable System Verilog RTL and documentation that others can build on.
• Drive the full front-end design flow — lint, CDC, synthesis, timing, and debug — and own your block through to tape out.
• Participate in design reviews, contribute ideas to improve logic architecture, and help refine design best practices.
• Debug simulatio

📌 Senior RTL Design Engineer (Bengaluru)
🏢 CScale
📍 Bengaluru