SoC-level verification of high-speed interface IP, including test porting, regression and silicon bring-up support.
Skills Looking For
• SystemVerilog, UVM/OVM, constrained random verification
• SoC-level integration and test porting
• RTL, GLS and timing simulation debug
• Testbench bring-up and third-party VIP integration
• Working knowledge of USB, PCIe, UFS, MIPI, DDR and loopback tests
• Python, Perl or Tcl scripting (plus)