We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in the trenches of formal verification, and you know the difference between a proof that closes and one that explodes the state space at 2am. You understand that formal is not magic, it is a precise tool that works brilliantly when applied to the right problem with the right setup, and you have developed the instinct to know which is which.
You are comfortable walking into a customer's verification workplace, looking at their design blocks and assertion strategy, and quickly seeing where formal will shine and where it will struggle.
Diagnosing why a formal run is slow or why convergence stalled does not frustrate you, it engages you. You think in terms of abstraction, state space, and proof complexity, and you can refactor a formal testbench so the tool can actually finish.
At Synopsys, you will work directly with customers deploying VC Formal across complex SoC and IP designs, and what you recommend will directly shape how they verify their next chip.
What You'll Be Doing
• Lead technical deployment of VC Formal at customer sites, assessing their verification environments and recommending formal methodologies that fit their design challenges
• Analyze customer design blocks to identify the right candidates for formal property checking, sequential equivalence, connectivity checking, and formal coverage analysis
• Diagnose root causes of tool performance issues and design complexity bottlenecks, then optimize formal testbench modeling to achieve proo