EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge's robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today's best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in **** and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Staff / Senior Staff Engineer: Static Timing Analysis (STA) Lead.
We are seeking a high-caliber
Staff or Senior Staff Engineer
to lead SOC Timing Convergence. This is a critical leadership role for a driven,
"go-getter"
engineer who excels at navigating the complexities of modern, large-scale SOC designs. You will be the bridge between Architecture, RTL, DFT, and Physical Design to ensure a predictable, high-performance path to tape-out.
The Role
As a lead for SOC Timing or SubChip Timing, you will own the strategy for convergence. You will identify bottlenecks early in the design cycle ("left-shifting") and drive cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets.
Key Responsibilities
Timing Convergence Leadership:
Drive full-chip SOC timing closure across all corners and modes (func, shift, capture, etc.).
Cross-Functional Coordination:
Partner with
Architecture
to validate timing feasibility,
RTL
to optimize logic structures, and
DFT
to streamline test-mode timing.
Left-Shift Strategy:
Proactively identify and resolve structural timing issues, congestion,



and high-latency paths early in the RTL/Synthesis phase to ensure predictable physical design execution.
Advanced Analysis:
Perform complex timing tasks including
CPPR/CRPR
analysis,
NoC
(Network-on-Chip) timing, and constraint validation (SDC).
Automation & Agility:
Architect and build sophisticated automation utilities (Tcl, Python, Perl) to accelerate timing sign-off, reduce manual audits, and improve schedule agility.
PPA Optimization:
Drive best-in-class PPA by guiding physical design teams on floorplanning, clock tree synthesis (CTS) strategies, and placement optimizations.
Requirements & Qualifications
Experience:
9 to 14 years of hands-on experience in STA and Timing Closure on advanced process nodes (7nm, 5nm, or below).
Critical Thinking:
Proven ability to debug complex timing violations, identify root causes (e.g., data-to-clock skew, crosstalk), and propose architectural or physical solutions.
Technical Mastery:
* Expertise in industry-standard sign-off tools (e.g., PrimeTime, Tempus). Preferable Tempus tool.
Deep understanding of
Multi-Mode Multi-Corner (MMMC)
challenges and Hierarchical vs. Flat timing closure.
Proficiency in SDC/CDC constraints.
Soft Skills:
Solid leadership presence with the ability to influence cross-functional teams and drive execution in a fast-paced environment.
Education:
B.Tech/M.Tech
in Electrical/Electronics Engineering or a related field.
Why Join Us?
You will have the autonomy to define the timing methodology for next-generation silicon. This role offers the opportunity to tackle the industry's toughest frequency and power challenges while building the automation infrastructure that defines our engineering excellence.

📌 Staff / Senior Staff Engineer: Static Timing Analysis (Sta) Lead (Bengaluru)
🏢 Enchargeai
📍 Bengaluru