Experience: 10+ Years of experience

Role: Mixed Signal DFT lead/engineer

Role Overview

We are looking for an experienced DFT Engineer with 10+ years of semiconductor industry experience and solid hands-on expertise in DFT verification of mixed-signal blocks, Pattern debug on ATE, and Tessent-based pattern generation.

The ideal candidate will have a solid understanding of mixed signal IP like SERDES, Sensors, non-volatile memory (effuse/otp/), JTAG/iJTAG architectures, PDL development for Pattern development, in-depth understanding on ATE and The candidate should be capable of independently debugging complex DFT and production-test issues and driving them to closure.

Key Responsibilities
Perform DFT verification of mixed-signal IP blocks in complex SoC
Own verification and debug of DFT features across block and SoC levels.
Develop, verify, and debug ATE test patterns and drive pattern bring-up on silicon.
Perform ATE pattern debug and stabilization, including root-cause analysis of simulation-to-silicon and tester-related failures.




Work extensively with JTAG (IEEE 1149.1) and iJTAG (IEEE 1687) architectures and associated verification flows.
Develop and maintain PDL (Procedural Description Language) for embedded instruments and iJTAG networks.
Generate, validate, and debug DFT patterns using Siemens Tessent tools.
Debug complex pattern, timing, protocol, and DFT infrastructure issues across simulation and ATE settings.
Collaborate closely with DFT, design, verification, physical design, product engineering, and test engineering teams during pre-silicon and post-silicon phases.
Drive technical issues independently from initial investigation through root-cause identification and final resolution.

Required Skills & Experience
10+ years of hands-on experience in DFT, DFT verification.
Strong hands-on experience with verification of mixed-signal blocks from a DFT perspective.
In-depth understanding of ATE architecture, test programs,

📌 Senior Dft Engineer Bengaluru
🏢 ARM
📍 Bengaluru