Job DescriptionWe are looking for an experienced Senior ASIC RTL Design Engineer to join our growing semiconductor design team. The ideal candidate will have robust experience in RTL development, micro-architecture design, and SoC integration.
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nLocation: Bangalore/Hyderabad
NExperience: 8–15 Years
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nKey Responsibilities:
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Design and develop synthesizable RTL using Verilog/System Verilog
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Translate architecture specifications into micro-architecture and RTL implementation
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Develop high-performance and low-power digital design blocks
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Work closely with verification teams for functional validation and debug
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Perform design reviews and ensure coding quality and design guidelines
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Collaborate with physical design teams to meet timing, power, and area requirements
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Debug RTL issues and support silicon bring-up when required
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nRequired Skills:
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Strong expertise in Verilog and System Verilog
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Solid understanding of digital design fundamentals and computer architecture
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Experience with AMBA protocols such as AXI,
AHB, and APB
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Knowledge of synthesis,timing closure, and low-power design techniques
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Familiarity with simulation and debugging tools
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Experience working in ASIC/SoC design environments
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nPreferred Qualifications:
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Solid debugging and problem-solving skills
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Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
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Solid understanding ofdigital logic design principles.
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nAbout us:
NTessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a