Job DescriptionAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
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This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables. N
Mentoring junior engineers and driving innovation/automation. N
BE/B.Tech/M.E/M.Tech with 3+ years of relevant work experience and strong understanding of DFT concepts and good communication skills. N
Robust hands-on experience using industry standard EDA Tools. N
Experience with logic simulators from one or more EDA vendors. N
Experience on industry standard ATPG tools like Cadence Modus. N
Experience with RTL lint tools like Jasper. N
Experience in scan insertion,



coverage analysis and debugging skills on faults coverage enhancement is required. N
Programming in Perl/Tcl/Python or other scripting languages is a plus. N
Experience in post silicon validation, ATE debug and support is desired. N
Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop. N
Positive understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus. N
Participate in driving current DFT methodology and solutions to improve quality, reliability and in-system test and debug capability. N

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📌 Lead Dft Design Engineer Bengaluru
🏢 Cadence System Design and Analysis
📍 Bengaluru