EMIR / Power Integrity Engineer (India)

EMIR / Power Integrity Engineer (India)

09 Oct
|
Aion Silicon
|
India

09 Oct

Aion Silicon

India

We are seeking a skilled EMIR / Power Integrity Engineer to join our SoC Physical Design team. The ideal candidate will be responsible for power delivery network (PDN) planning, power integrity analysis, EMIR verification, and signoff for advanced semiconductor designs. The role involves ensuring reliable power delivery across the chip through static and energetic IR drop analysis, electromigration verification, power grid optimization, and ECO implementation to achieve signoff-quality designs.

Key Responsibilities
• Perform Power Integrity and EMIR analysis for complex SoC, subsystem, and IP designs.

• Develop, analyze, and optimize Power Delivery Networks (PDN) to meet performance, power, and reliability requirements.

• Execute Static IR Drop, Dynamic IR Drop, and Electromigration (EM) analysis throughout the design cycle.

• Define simulation methodologies, run setups, and signoff criteria for power integrity verification.

• Develop and enhance CAD-based EMIR analysis flows incorporating timing, package, and board-level abstractions.

• Identify, debug, and root-cause EM,



Static IR, and Dynamic IR violations.

• Provide and implement ECO solutions to resolve power integrity violations, including power grid enhancements, strap optimization, cell spreading, decap insertion, power routing improvements, and layout modifications.

• Validate ECO effectiveness through iterative EMIR analysis and drive complete signoff closure.

• Collaborate closely with Physical Design, CAD, RTL, Package, and Reliability teams to achieve power integrity goals.

• Automate analysis, debugging, and reporting flows using Tcl, Python, Perl, or Shell scripting.

• Support advanced technology nodes and contribute to methodology development and continuous improvement.

Required / Preferred Qualifications
• Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.

• 5+ years of ASIC/SoC EMIR experience.

• Knowledge of UPF and low-power design methodologies.

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📌 EMIR / Power Integrity Engineer (India)
🏢 Aion Silicon
📍 India

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