09 Oct
|
Samniya Techsys
|
India
09 Oct
Samniya Techsys
India
Job Description :
Own partition floorplanning for optimizing blocks for Power, Performance and Area.
Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
Have close collaboration with RTL team to help drive and resolve design issues related to block closure.
Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
Implement robust clock distribution solutions using appropriate methods that meet design requirements.
Make positive independent technical trade-offs between power, area, and timing (PPA)
Skills:- VLSI, RTL and EMIR
📌 Physical Design Engineer (India)
🏢 Samniya Techsys
📍 India