09 Oct
|
Aion Silicon
|
India
09 Oct
Aion Silicon
India
We are seeking a highly motivated Principal STA / Constraints Sign-Off Engineer to lead timing signoff and constraint methodology development for advanced-node SoC and IP designs. The ideal candidate will have deep expertise in STA, timing constraints, signoff closure, and methodology automation, enabling successful tape-outs with best-in-class quality, performance, power, and area (PPA).
This role requires a solid hands-on technical leader who can drive methodology, execution, and signoff while collaborating closely with Architecture, RTL, Verification, DFT and PD team collaboration.
Key Responsibilities
• Own and drive SoC/IP/blocks timing signoff methodologies across advanced technology nodes.
• Develop, review, and validate SDC constraints, timing exceptions, and MMMC signoff environments.
• Lead setup, hold, SI, OCV/AOCV/POCV, and timing closure activities through final signoff.
• Drive timing correlation across synthesis, implementation, extraction, and signoff flows.
• Support ECO closure, low-power timing analysis, and cross-functional signoff activities.
• Develop automation scripts, methodology documentation, training materials, and best practices.
• Collaborate closely with RTL, Physical Design, DFT, CAD, Verification, and IP teams to achieve timing convergence.
Required / Preferred Qualifications
• BS/MS in Electrical Engineering or related field with 12+ years of experience in STA, timing signoff, and ASIC/SoC implementation.
• Strong hands-on expertise in PrimeTime, SDC development, MMMC analysis, timing closure, OCV/AOCV/POCV, crosstalk, and ECO methodologies.
• Good understanding of ASIC implementation flows, libraries, memories, PDKs, and advanced-node signoff requirements.
• Strong scripting skills in Tcl, Python, or Perl for flow automation and methodology development.
• Excellent debugging, analytical, communication, and technical leadership skills.
• Experience with advanced-node technologies (7nm/5nm/3nm and below).
• Knowledge o
📌 Principal Engineer – STA (India)
🏢 Aion Silicon
📍 India