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PMTS SILICON DESIGN ENGINEER

? THE ROLE
As a PHY‑V Lead, you will own physical verification sign-off, full-chip integration, and packaging interface (RDL) planning for advanced SoC programs. You will drive DRC/LVS clean tapeouts, integration quality, and sign-off predictability across complex multi-IP designs.
This role requires strong expertise in physical verification, top-level integration, and advanced packaging alignment, along with the ability to lead cross-functional execution across PD, Analog, and Packaging teams.

? THE PERSON




• Strong technical leader with deep PD + Physical Verification understanding
• Proven ownership of sign-off closure for complex SoCs
• Ability to drive execution across multiple teams and dependencies
• Detail-oriented with focus on quality, manufacturability, and schedule predictability
• Comfortable operating in high-pressure tapeout environments

? KEY RESPONSIBILITIES
✅ Physical Verification & Sign-off Ownership
• Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level
• Define and enforce sign-off methodology and quality criteria
• Own foundry rule decks, waivers, and risk assessments
• Deliver sign-off clean GDS for tapeout

✅ SoC / Full-Chip Integration
• Lead top-level integration of IPs/macros into SoC
• Own:
• GDS assembly
• Hierarchical LVS reconciliation

• Resolve:
• Boundary issues
• Connectivity mismatches
• Integration conflicts

• Ensure robust integration

📌 PD Lead (Hyderabad)
🏢 Advanced Micro Devices
📍 Hyderabad