09 Oct
|
smartsoc solutions
|
Bengaluru
09 Oct
smartsoc solutions
Bengaluru
Experience: 3–8 Years
Location: Hyderabad,
Key Responsibilities
• Execute Gate-Level Simulations (GLS) with zero-delay and SDF timing.
• Debug setup/hold, recovery/removal, X-propagation, and timing violations.
• Validate RTL-to-gate equivalence and synthesis/P&R; impacts.
• Perform SoC-level GLS for boot, reset, clocks, interrupts, and functional scenarios.
• Verify low-power features such as UPF, isolation, retention, and level shifters.
• Validate DFT/scan/ATPG/JTAG functionality at gate level.
• Debug failures using VCS/Xcelium/Questa, Verdi/DVE and waveform analysis.
• Correlate GLS failures with STA, RTL, synthesis, PD, and DFT results.
• Automate GLS regressions using Python/Perl/Tcl/Shell.
• Support pre-silicon signoff and tape-out readiness.
📌 GLS Verification Engineer (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru