Company: www.prajnov.com
Title: Design Verification Lead
Experience: 6+ years
? Key Skills:
• Solid SystemVerilog & UVM experience on live projects
• Expertise in AMBA protocols & ARM CPU
• Functional verification using Monitors, Checkers, Scoreboards & Assertions
• Constrained-random verification & functional coverage
• Strong debugging & problem-solving skills
• Unix/Linux and verification tools for configuration management, bug tracking & dashboards
• Scripting: Python / Perl / Shell / Makefile
• PCIe / Ethernet experience is an added advantage
? Locations: Kochi | Chennai | Bangalore | Pune
?Share resume:
[email protected]
Hiring #DesignVerification #SystemVerilog #UVM #VLSI #ASIC #SoC #Semiconductor #Verification #AMBA #ARM #PCIe
📌 Design Verification lead (Bengaluru)
🏢 Prajnov
📍 Bengaluru