Role Description
Who we are:
At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .
Summary
UST is looking for a SoC Verification Engineer with strong expertise in SystemVerilog, UVM, and coverage-driven verification for complex IP and SoC designs.
The Chance
We are seeking an experienced SoC Verification Engineer to drive the verification of complex digital subsystems and full-chip SoCs. The ideal candidate will be responsible for developing robust verification environments, executing comprehensive verification plans, and collaborating closely with design and architecture teams to ensure high-quality silicon delivery.
Key Responsibilities
• Develop and execute comprehensive SoC and IP verification plans
• Build, maintain, and enhance verification environments using UVM/OVM/VMM methodologies
• Develop testbenches including stimulus generation, monitors, constraints, assertions, scoreboards, and checkers
• Create directed and constrained-random test scenarios to validate functional correctness
• Perform coverage analysis and drive functional and code coverage closure
• Debug simulation failures, perform root-cause analysis, and drive issue resolution
• Collaborate with RTL design and architecture teams to resolve functional issues
• Enhance verification methodologies, automation, and reusable verification components
• Document verification results, review metrics, and provide regular project status updates
• Participate in design reviews and code reviews, providing technical feedback and recommendations
Required Qualifications
• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline
• 5+ years of experience in IP an
📌 Technical Lead I (Bengaluru)
🏢 UST
📍 Bengaluru