JD
STA, Timing Closure is must
Veena Johar is looking for profiles, with some PD experience, like Placement and Routing (PnR), Static Timing Analysis (STA) along with TCL scripting with 3+ years of experience along with FPGA Design.
• BS or MS in EE or CE with 3+ years of experience in digital design and/or timing closure.
• Strong background in RTL design using Verilog/VHDL.
• Timing Constraints (SDC) & Static Timing Analysis .
• Solid understanding and usage of ASIC and/or FPGA software tool
chain like Vivado or Quartus.
• Strong Digital Design Fundamentals and applications
• TCL Scripting language
• • Applications and Designs in Wireless/Wired domain.ior experience in STA or physical design in the semiconductor industry preferred.
• Experience with advanced technology nodes, multi-mode multi-corner analysis, ECO flows, and timing sign-off for high-performance or low-power designs is beneficial.

Location- Bangalore, Hyderabad and Noida
Share resume to [email protected]
Exp-3+ years

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