Position: Design Verification Engineer (SystemVerilog/UVM) (BB50FT RM 4458)

- Candidate Skill: IP/Block/Subsystem Verification, RTL Front-End Verification
o Years of Experience/Expectations: Minimum 5 Years
o Mandatory/Optional: Mandatory
- Candidate Skill: SystemVerilog (SV), UVM Verification, UVM Testbench Development
o Years of Experience/Expectations: Minimum 4 Years
o Mandatory/Optional: Mandatory
- Candidate Skill: AXI, AHB Interfaces, Bus Protocol Verification
o Years of Experience/Expectations: Minimum 2 Years
o Mandatory/Optional: Mandatory
- Candidate Skill: PCIe, NVMe Protocol Verification
o Years of Experience/Expectations: Minimum 1 Year
o Mandatory/Optional: Mandatory
- Candidate Skill: Perl, Python Scripting, Verification Automation
o Years of Experience/Expectations: Minimum 1 Year
o Mandatory/Optional: Optional

Job Description

- An expert level experience with PCIe IP/sub-systems.
- AXI protocol is mandatory
- Highly experienced with defining block, sub-system.
- An expert level with developing UVM-based SV test-benches.
- Deep understanding and knowledge of verification methodologies flows and quality metrics.
- Great debugging and problem-solving skills.




- Team player with excellent interpersonal communication skills.

Job Qualifications

- At least 3-6 years of relevant experience in PCIe verification.
- Strong and relevant expertise with ASIC simulation tools and advanced verification methods.
- Expert level in verification languages such as UVM and System Verilog.
- Relevant experience with writing block-level .
- Education: B.S. in electrical engineering, computer science with extensive industry experience.

Skills Required:

- IP/Block/Subsystem Verification (RTL Front end verification) - minimum 5 years
- SV, UVM Verification - minimum 4 Years
- Interfaces (AXI/AHB) - minimum 2 years
- Protocols (DDR/Onfi/PCIE/NVMe) - minimum 2 years
- Scripting (Perl/Python) - Optional

Job Category: Others

Job Type: Full Time

Job Location: Bangalore Hyderabad

Experience: 5+ years

Notice period: 0-30 days

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Design Verification Engineer (SystemVerilog/UVM) (Hyderabad)
🏢 Sourceright Technologies
📍 Hyderabad