09 Oct
|
HC Robotics
|
Kolkata
09 Oct
HC Robotics
Kolkata
Graduate Engineer Trainee VLSI / RTL Design
Location: Kolkata
Experience: 0 - 3 Years
Qualification:
- B.E./B.Tech/M.Tech in ECE, EEE, EIE, VLSI & Microelectronics, or related disciplines
- VLSI/RTL Design training preferred
Skills Required:
- Digital Electronics & RTL Design
- Verilog HDL, SystemVerilog Basics
- FSM Design, Combinational & Sequential Logic
- RTL Simulation & Debugging
- Basic FPGA Design Flow
Preferred Skills:
- ASIC Design Flow, Vivado
- STA & Synthesis Concepts
- UVM Fundamentals
- TCL Scripting, Linux, Git
Role: Develop and debug RTL designs using Verilog/SystemVerilog, perform simulations, support FPGA prototyping, assist in synthesis and timing closure activities, and collaborate with design and verification teams.
Ideal Candidate: Freshers or candidates with up to 3 years of experience, robust digital design fundamentals, hands-on RTL/VLSI training or projects, and a passion for ASIC/FPGA design.
📌 Graduate Engineer Trainee - VLSI or RTL Design (Kolkata)
🏢 HC Robotics
📍 Kolkata