As a member of IO & PHY Group, you will help develop layout designs. As a member of the team, you will work closely with the architecture, IP design, Physical Design teams to achieve first pass silicon success.
The Person
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing positive communication and problem-solving skills.
Key Responsibilities
- Implementation Layout of blocks and macros
- Own and deliver the high-quality macros with help of team
- Mentor and groom the juniors in the team
- Work with contractor team and the planned work done as per aligned schedule
- Enable release flows as required
Preferred Experience
- 8+ yrs of hands-on experience in layout design
- Experience with Cadence virtuoso, Caliber and other verification tools as required for layout development
- Preferrable experience in high speed SERDES blocks
Academic Credentials
Bachelors or Masters degree in Electrical Engineering or equivalent
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