MTS Timing Constraint Development Engineer

The focus of this role is to plan and develop the Timing constraints of IPs Subsystem or Full chip. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also expand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.

Key Responsibilities

- Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools.
- Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
- Collaborate with designer and PNR teams to achieve closure.
- Understand duration required, plan and execute as per schedule.
- Complete quality delivery for synthesis and timing closure.
- Debug and resolve technical issues

Preferred Experience





- Existing SDC, constraints development with or without using fisthail, excellicon or TCM.
- Experienced in synthesis, LEC, CLP and timing closure
- Preferred top level or SOC level experience
- Have handled blocks with complex designs, high frequency clocks and complex clocking
- complete understanding of timing constraints, low power aspects and concepts of DFT
- Have debug experience to solve issues.
- Interst in AI, Scripting and automation

Academic Credentials

- Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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