Job Summary

We are seeking a senior design manager in India for a rare opportunity to help build something foundational. We are looking for a recognized hands-on technical leader who can shape architecture, guide complex semiconductor development programs, solve challenging engineering problems, and make critical technical decisions, while being able to attract exceptional talent, mentor engineers, and build a high-performing organization from the ground up. This is a unique opportunity to help establish and scale CBU s Silicon Design Center in India while defining both the technical direction and engineering culture of the organization.

Responsibilities

- Strategic Leadership and Talent Team Management:
- Lead and develop a team of 20+ engineers;
- Manage resource allocation, performance reviews, and technical career growth.

- Technical Execution :

- Drive end-to-end RTL design execution, from concept through to architecture, coding, verification, synthesis, sign-off, and silicon bring-up support;
- Serving as a technical authority for digital design, ensuring high standards in quality, performance, power, and area;
- Resolving complex, cross-domain design and EDA tool challenges impacting schedule or silicon quality.

- Methodology Innovation:

- Drive the adoption of advanced techniques through different phases of silicon development: from design, verification, to validation and release to production;
- Continuously improve efficiency through automation, scripting, and the integration of AI-driven tools.

- Cross-Functional Collaboration:





- Partner closely with Physical Design, Software, Product Engineering, Validation and other teams/vendors to resolve complex integration issues and bottlenecks.

Requirements/Qualifications

- Education: Degree in EE (Bachelor's or higher)
- Work experience: 14+ years of experience is preferred
- Proven leadership skills with robust coaching and mentoring temperament
- Ability to think both strategically and tactically
- Deep understanding of all phases of silicon development with expertise in RTL design and verification.
- Strong understanding of functional verification flows and environments.
- Proven success delivering multiple complex tape-outs in high-performance silicon.
- Deep hands-on experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis along with physical design interactions.
- Solid experience with low-power design methodologies and flows.
- Working knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.
- Experience with Synopsys or Cadence tools for synthesis, verification or STA (an asset)
- Experience with 28nm and smaller silicon process technologies (an asset)
- Hands-on experience with ASIC EDA tools/environment is an asset.

Travel Time: 0% - 25%

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Senior Manager - Design Engineering (Bengaluru)
🏢 Microchip Technology
📍 Bengaluru