10 Oct
|
smartsoc solutions
|
India
10 Oct
smartsoc solutions
India
Location: Bangalore
Experience: 5+yrs
• PCIe Gen5/Gen6: Knowledge of high-speed PCIe architecture, link training, LTSSM, speed/width negotiation, resets, and error handling.
• TL (Transaction Layer): Verify TLPs, Memory/Config transactions, completions, ordering, tags, and flow control.
• DL (Data Link Layer): Verify DLLPs, ACK/NAK, sequence numbers, replay, CRC/LCRC, and error recovery.
• PHY: Verify LTSSM, lane training, link width/speed, equalization, and recovery.
• UVM from scratch: Build the setting including agents, drivers, monitors, sequencers, scoreboard, assertions, coverage, tests, and regression.
• Debug: Analyze failures using waveforms, protocol logs, and UVM reports.
• Experience working with either connectivity protocols or high speed protocols.
📌 Design Verification Engineer (India)
🏢 smartsoc solutions
📍 India