Jb details

Engineering / Physical Design

India

Full time

Hybrid

We are seeking a highly mtivated Principal STA / Cnstraints Sign-Off Engineer t lead timing signff and cnstraint methdlgy develpment fr advanced-nde SC and IP designs. The ideal candidate will have deep expertise in STA, timing cnstraints, signff clsure, and methdlgy autmatin, enabling successful tape-uts with best-in-class quality, perfrmance, pwer, and area (PPA).

This rle requires a strng hands-n technical leader wh can drive methdlgy, executin, and signff while cllabrating clsely with Architecture, RTL, Verificatin, DFT and PD team cllabratin.

Key Respnsibilities

- Own and drive SC/IP/blcks timing signff methdlgies acrss advanced technlgy ndes.

- Develp, review, and validate SDC cnstraints, timing exceptins, and MMMC signff envirnments.

- Lead setup, hld, SI, OCV/AOCV/POCV, and timing clsure activities thrugh final signff.

- Drive timing crrelatin acrss synthesis, implementatin, extractin, and signff flws.

- Supprt ECO clsure, lw-pwer timing analysis, and crss-functinal signff activities.

- Develp autmatin scripts, methdlgy dcumentatin, training materials, and best practices.

- Cllabrate clsely with RTL, Physical Design, DFT, CAD, Verificatin, and IP teams t achieve timing cnvergence.

Required / Preferred Qualificatins





- BS/MS in Electrical Engineering r related field with 12+ years f experience in STA, timing signff, and ASIC/SC implementatin.

- Strng hands-n expertise in PrimeTime, SDC develpment, MMMC analysis, timing clsure, OCV/AOCV/POCV, crsstalk, and ECO methdlgies.

- Gd understanding f ASIC implementatin flws, libraries, memries, PDKs, and advanced-nde signff requirements.

- Strng scripting skills in Tcl, Pythn, r Perl fr flw autmatin and methdlgy develpment.

- Excellent debugging, analytical, cmmunicatin, and technical leadership skills.

- Experience with advanced-nde technlgies (7nm/5nm/3nm and belw).

- Knwledge f UPF, lw-pwer design, EMIR, and thermal signff flws.

- Familiarity with high-speed prtcls such as PCIe, DDR, UCIE,ABB, PLLs and all latest IPs.

- Experience driving methdlgy imprvements and mentring engineering teams.

Tls Required:

- Synpsys: PrimeTime (PT/PT-SI/PT-PX), ICC2/Fusin Cmpiler, StarRC, and ICV fr STA, signff, implementatin, extractin, and physical verificatin.

- Cadence: Tempus, Innvus, and Vltus fr timing analysis, physical implementatin, and pwer integrity signff.

- Scripting: Strng prficiency in Tcl, Pythn, and Perl fr autmatin, methdlgy develpment, and reprting.

📌 Principal Engineer – STA / Constraints Sign-Off Engineer (India)
🏢 Aion Silicon
📍 India