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Experience: 3+ yrs

Location: Remote (India), India

Job Type: Full-time

We are looking for an experienced ASIC / FPGA Design Engineer with strong hands-on expertise in digital design, RTL development, verification, and implementation flows. The ideal candidate will have practical experience taking chip designs from specifications and RTL through verification, synthesis, physical design, and timing closure.

This role combines semiconductor engineering expertise with the development of technical evaluations for AI systems. You will create realistic engineering tasks, develop reference solutions, assess AI-generated designs, and identify functional, timing, and power-performance-area (PPA) issues. The focus is on applying real-world engineering judgement to evaluate how effectively AI agents perform complex chip-design tasks.

Requirements

Key Responsibilities
- Develop realistic engineering evaluation tasks covering RTL design, functional verification, synthesis, physical design,



and sign-off.
- Write reference implementations in Verilog, SystemVerilog, or VHDL, supported by testbenches, constraints, and expected results.
- Define transparent grading criteria and validation methods that reflect industry-standard engineering expectations.
- Review AI-generated RTL, testbenches, hardware designs, and implementation results to identify functional errors and design weaknesses.
- Diagnose verification failures, coverage gaps, timing violations, and suboptimal power, performance, and area decisions.
- Evaluate designs against functional correctness, timing constraints, resource utilisation, and implementation quality.
- Configure and maintain EDA-based environments that enable AI agents to execute realistic chip-design workflows.
- Work with tools from Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, or Intel Quartus, as relevant to the evaluation.
- Develop tasks that asses

📌 FPGA Engineer (India)
🏢 Weekday AI
📍 India