Lead Analog (Vijayawada)

Lead Analog (Vijayawada)

10 Oct
|
Qailash Labs
|
Vijayawada

10 Oct

Qailash Labs

Vijayawada

• Role Level: Core Engineering (Senior AMS Circuit Designer / Analog Lead)
• Location: Vijayawada (AP) / Hybrid (Flexible)
• Experience: 4+ years of dedicated hands-on experience in Transistor-Level Custom AMS Circuit Design with proven tape-out closure (or graduating M.Tech/Ph.D. with relevant silicon converter/front-end research)

APPLICANT SCOPE & SCREENING NOTICE (PLEASE READ CAREFULLY):
Strictly Custom Silicon IC Design: This position requires transistor-level schematic design, device sizing, and SPICE simulation of custom analog blocks in Cadence Virtuoso / Spectre.
Non-Applicable Profiles: Candidates whose experience is limited to standard cell library characterization (.lib modeling), automated digital RTL/FPGA implementation, or board-level (PCB) circuit design are not suitable for this silicon IC design role.

Role Overview:
Lead custom transistor-level schematic design, precision sizing, compact SPICE model verification, and AMS simulation of low-noise sensor front-ends, high-resolution column data converters,



and precision power/bias management circuits on advanced deep-submicron CMOS and SOI process nodes. Working in close collaboration with our Silicon Architects and Custom Layout Engineers, you will own critical mixed-signal blocks from architectural definition through schematic sizing, Monte Carlo verification, and post-layout parasitic extraction (PEX) sign-off.

Key Responsibilities:
Sensor Front-End Design: Architect, size, and simulate low-noise Capacitive Transimpedance Amplifiers (CTIA), Direct Injection (DI), Buffered Direct Injection (BDI), and Correlated Double Sampling (CDS) noise-filtering stages to achieve ultra-low input-referred noise and wide energetic range.
Column-Parallel Data Converters: Design high-resolution (12-bit to 14-bit), low-power column-parallel SAR ADCs operating within tight column-pitch constraints; implement asynchronous SAR timing control logic, monotonic/split-capacitor CDAC switching topologies, and dynamic comparato

📌 Lead Analog (Vijayawada)
🏢 Qailash Labs
📍 Vijayawada

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