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Senior Design Verification Engineer

A global semiconductor organisation with a design centre in Bengaluru

• LOCATION Bengaluru, Karnataka
• TYPE Permanent
• EXPERIENCE 6–10 years
• REFERENCE VYS-SEM-041

About The Role

What this role is.

Apply for this role

Our client is building out a verification team for a new SoC programme. This is a hands-on senior role with scope to influence methodology, not a headcount fill.

The team is small and the silicon is complex. You would own verification for one or more sub-systems end to end, from testplan through to sign-off.

What you'll do

Responsibilities.

• Own the verification testplan for assigned sub-systems
• Build and extend UVM testbench components and sequences
• Drive coverage closure — functional, code and assertion
• Debug failures with the design team and take them to root cause
• Contribute to methodology and regression infrastructure

What we're looking for

Essential.





• 6+ years in ASIC or SoC design verification
• Robust SystemVerilog and UVM
• Demonstrable coverage-driven verification experience
• At least one silicon tape-out you were personally accountable for
• Comfortable owning debug through to root cause

Nice to have

• Formal verification exposure
• Low-power or UPF verification
• Scripting in Python or Perl for regression tooling

What this role offers

Why it's worth a conversation.

• A sub-system you own outright rather than a slice of someone else's testplan
• A design team in the same building, not across timezones
• Methodology input — this team is still shaping how it works

How to apply

One step.

Send your CV quoting reference VYS-SEM-041. One of our founders reviews every application personally.

Your application is confidential. We will not share your details with the hiring organisation without discussing the role with you first.

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Posted 4 August 2026

📌 Senior Design Verification Engineer (Bengaluru)
🏢 Vysmira Solutions
📍 Bengaluru