DTMA & Memory Controller Design Lead (Bengaluru)

DTMA & Memory Controller Design Lead (Bengaluru)

10 Oct
|
L & T Case Equipment Private
|
Bengaluru

10 Oct

L & T Case Equipment Private

Bengaluru

LNT/D-MCDL/1889962

• LTST-L&T; Semiconductor Technologies Limited
• Bengaluru - L&T; Tech Park S2
• Posted On09 Oct 2026
• End Date07 Apr 2027
• Required Experience10 - 18 years

Skills

Knowledge & Posting Location

RTL

Minimum Qualification

BE

Job Description

DTMA & Memory Controller Design Lead Location: Bangalore, India | Company: LTSCT — L&T; Semiconductor Technologies Limited Reporting To: Chandra — Senior Architect, DC HW Systems | Experience: 10+ years (mandatory) Role Summary The DTMA & Memory Controller Design Lead owns the Data Transfer and Memory Access (DTMA) engine together with HBM4e memory-controller integration. You will orchestrate all data movement between the 512-bank SRAM (8 TB/s), the 6-stack HBM4e subsystem (384 GB, 12 TB/s), and the PE arrays — the subsystem that keeps xPU's compute engine saturated. Key Responsibilities

• Own micro-architecture and RTL of the DTMA engine managing data movement between SRAM banks, HBM4e, and the BFOS PE arrays.




• Define the compute-to-memory interface with the DTMA engine and SRAM banks to keep PE arrays fully fed at bandwidth.
• Lead integration and configuration of HBM4e memory controllers across 6 stacks (384 GB, 12 TB/s aggregate).
• Design descriptor-based DMA, gather/scatter, tensor-tiling, and prefetch mechanisms optimized for BFOS dataflow.
• Architect the 512-bank, 8 TB/s SRAM access scheduling, bank arbitration, and conflict-avoidance logic.
• Optimize address mapping, request scheduling, and refresh/timing to maximize sustained HBM bandwidth efficiency.
• Define QoS and flow-control interfaces to the NoC and compute engine to prevent stalls and starvation.
• Drive verification, performance modeling, and bandwidth/latency closure across realistic AI workload traffic.
• Collaborate with PD on HBM PHY/controller placement and with architecture on memory-hierarchy trade-offs. Required Skills & Experience
• 10+ years in memory-subsystem, DMA, or memory-controller design for high-bandwidth SoCs.
• Dee

📌 DTMA & Memory Controller Design Lead (Bengaluru)
🏢 L & T Case Equipment Private
📍 Bengaluru

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