Jb details

Engineering / Physical Design

India

Full time

Hybrid

We are seeking a highly mtivated Senir Methdlgy Engineer t drive the develpment f advanced Physical Design autmatin, methdlgies, and quality systems fr cmplex SC and ASIC designs. The ideal candidate will cmbine strng expertise in the RTL-t-Signff Physical Design flw with sftware develpment skills t build scalable autmatin framewrks, imprve design prductivity, and enable high-quality silicn delivery acrss advanced prcess technlgies.

Key Respnsibilities

- Develp and maintain autmatin framewrks supprting the cmplete RTL-t-Signff Physical Design flw.

- Build methdlgy slutins fr synthesis, flrplanning, pwer planning, placement, CTS, ruting, timing clsure, and signff.

- Create quality checking, validatin, and reprting systems fr implementatin and signff metrics.

- Develp scalable tls, scripts, and data pipelines fr design analysis, prductivity enhancement, and methdlgy ptimizatin.

- Cllabrate with Physical Design, STA, DFT, RTL, Library, and CAD teams t imprve implementatin methdlgies and design quality.

- Drive cntinuus imprvements in timing, pwer, area, cngestin, IR/EM, and physical verificatin clsure.

- Define and maintain best practices, design guidelines, and signff methdlgies acrss multiple prjects.





- Supprt advanced-nde implementatin challenges thrugh innvative autmatin and data-driven slutins.

Required / Preferred Qualificatins

- Bachelr's r Master's degree in Electrical/Electrnics Engineering, Cmputer Engineering, r related field.

- 4+ years f experience in Physical Design, CAD Methdlgy, r Design Autmatin.

- Strng understanding f the cmplete ASIC/SC implementatin flw frm RTL t GDSII Signff.

- Experience develping autmatin slutins using Pythn, Tcl, Perl, Shell, r C++.

- Hands-n experience with industry-standard EDA tls and flw custmizatin.

- Experience with advanced technlgy ndes (7nm, 5nm, 3nm, r belw).

- Strng knwledge f hierarchical and tp-dwn design methdlgies.

- Experience in Physical Design flw autmatin, CAD infrastructure, and methdlgy develpment.

- Expsure t AI/ML r LLM-based slutins fr EDA autmatin and prductivity enhancement.

- Excellent prblem-slving, debugging, and crss-functinal cllabratin skills.

Tls & Skills

- Synpsys: Design Cmpiler (DC), Fusin Cmpiler (FC), IC Cmpiler II (ICC2), PrimeTime (PT),ICV, StarRC

- Cadence: Innvus, Tempus, Vltus, Pegasus

- Siemens/Mentr: Calibre DRC, LVS, ERC

- Prgramming: Pythn, Tcl, Perl, Shell, C++

- Autmatin: Wrkflw develpment, data pipelines, quality dashbards, methdlgy deplyment

📌 Senior Methodology Engineer – Physical Design Automation (India)
🏢 Aion Silicon
📍 India