Key Responsibilities

- End-to-end ASIC/SoC/IP verification activities.

- Define verification plans, methodologies, and sign-off criteria.

- Develop and review UVM/SystemVerilog-based verification environments.

- Drive verification execution, debugging, regression, and coverage closure.

- Collaborate with customers, design teams, and stakeholders to ensure successful project delivery.

- Ensure quality execution and delivery within project timelines.

Requirements

Required Skills

- 4-9 years of ASIC/SoC/IP Functional Verification experience.

- Solid hands-on expertise in SystemVerilog and UVM.

- Experience developing testbenches, sequences, scoreboards, monitors, drivers, and coverage models.

- Good understanding of constrained-random and coverage-driven verification methodologies.

- Experience with simulation,



debugging, regression, coverage analysis, verification planning, and sign-off.

- Strong knowledge of RTL design and digital design concepts.

- Experience with one or more protocols:

- AMBA AXI/AHB/APB

- PCIe

- Ethernet

- USB

- DDR

- GLS

Preferred Skills

- Python, Perl, or C/C++ scripting.

- Exposure to Formal Verification, Emulation, FPGA Prototyping, or Post-Silicon Validation.

- Experience working with global customers and distributed teams.

Education

- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related field.

📌 Senior Engineer/Lead Engineer- ASIC verification (Bengaluru)
🏢 SignOff Semiconductors
📍 Bengaluru