Senior Design Verification Engineer

Location: Bangalore/Hyderabad

Exp- 5 -12 yrs

NP - 0-30 days/Immediate

Role and Responsibilities: Domain: AXI, PCIe, UCIe protocol experience is highly preferred

- Must have experience in developing test benches for IP/Subsystems/SoC.
- In depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV.
- Previous experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities.
- Robust hands on experience with common verification tools and methodology including UVM/ System Verilog/CDV/MDV, DV signoffs.
- Must have a strong domain expertise in one or more following areas - AXI/PCIe/UCIe.
- Experience in Hybrid test benches (SV, SystemC, Python) and SystemC based reference model test vectors/stimulus based verification is desirable.

Interested candidates can share resume to [email protected]

📌 Senior Design Verification Engineer (Bengaluru)
🏢 ThunderSoft India Private
📍 Bengaluru