The focus of this role is to plan and execute the LEC and CLP of IP Subsystems and its signoff. This involves ownership of LEC and CLP at all physical partition level.
Key Responsibilities
- Responsible for LEC and CLP of all physical partitions of a device including its waivers, reviews and signoff
- Collaborate and support with design and/or implementation teams to achieve closure.
- Drive this activity with set of engineers by planning work and presenting regular status.
- Debug failure/issues and drive them to closure by working with CAD team or EDA vendor if required
Preferred Experience
- Highly Experienced in LEC and CLP with Synopsys or Cadence tool set.
- Complete Understanding of synthesis and Low power flows including UPF
- Have handled blocks with complex designs and their LEC/CLP lssues
- Have debug experience to solve issues.
- scripting and automation
Academic Credentials
- Bachelors with 6 years of experience or Masters degree with 4 year of experience in Electrical Engineering
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Role: Head - Hardware Engineering,
Industry Type: Electronic Components / Semiconductors,