Job Summary

Advance your career. Advance the world.

At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we'll advance your career.

MTS Full Chip STA (FCT) Silicon Design Engineer

Responsibilities

- As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. You will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.
- Owns Full chip Timing Closure
- Drive new improvement in closure
- Analysis of data and feedback to PD execution team
- SDC analysis and feedback
- Work with PnR engineer for timing convergence
- Drive the common STA methodology in the business unit
- Work and collaborate with different business units, CAD and central methodology team to drive the requirement
- Automation to refine and improve design signoff requirement and dashboarding
- Ability to organize and present complex technical information in a crisp and concise manner.
- Interact with other PPA (equivalent) teams internal to AMD
- Identify best practices across AMD and industry to update and improve flow/project settings
- To increase the competitiveness of each stage in AMD design flow
- Ability to work with multi-level functional teams across various geographies.




- Highly organized, robust affinity for automation and prioritization.

Preferred Experience

- Timing closure experience at SoC and block level
- Technical depth in STA, High freq interface closure in hierarchical STA.
- Multi voltage closure
- Timing ECO flow
- Hyperscale, Yield analysis
- PnR and STA signoff correlation drive and convergence
- Strong at SDC coding and debug skills
- Drive new requirements and methodology to aid timing closure at SoC
- Identify the gaps and support flows
- Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.
- Drive team towards common requirements and flows
- Experienced in deploying and implementing ML techniques and algorithms in physical design.
- Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
- Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
- AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.

Academic Credentials

- Bachelors with 7 years of experience or Masters degree with 5 years experience in timing

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

Role: Technical Lead, Industry Type: Electronic Components / Semiconductors, Department: Engineering - Software & QA, Employment Type: Full Time, Permanent Role Category: Software Development Education UG: Any Graduate PG: Any Postgraduate Key Skills design engineeralgorithmsphysical designpythondebugsoccadaiselection processartificial intelligencecadencehealthcarephysical verificationscriptingrtl designautomationddrserdescorrelationdashboardingperlml

📌 Full Chip Timing Lead (Hyderabad)
🏢 Advanced Micro Devices (AMD)
📍 Hyderabad