We are looking for DFT ENGINEERS

Experience 3- 8 Years

Location - Bangalore, Hyderabad

We are seeking a Staff DFT Engineer to own and drive the complete DFT strategy for complex SoCs from architecture through production silicon. The role requires deep hands-on expertise, strong technical judgment, and the ability to lead and mentor engineers while collaborating closely with design, PD, validation, and manufacturing teams.

The ideal candidate operates independently, makes architecture-level decisions, and is accountable for test quality, coverage, and silicon readiness.

Responsibilities

· Define chip/subsystem DFT architecture: scan, compression, LBIST, MBIST, boundary scan, test access

· Drive early RTL testability and balance coverage, test time, power, area, schedule trade-

offs

· Lead scan insertion, stitching, DFT DRC closure

· Execute ATPG (stuck-at, transition, path delay), compression, pattern optimization

· Own DFT signoff (coverage, IR drop, power, timing impacts)

· Debug DFT issues across RTL, synthesis, P&R;, and gate-level

· Generate/analyze ATPG patterns; sign off fault coverage, pattern volume, test time

· Diagnose coverage gaps and drive methodology fixes

· Support silicon bring-up, failure analysis, yield ramp

· Debug scan/BIST/tester failures; drive DFT ECOs

· Collaborate with ATE/manufacturing to improve yield and robustness





· Act as DFT technical lead; mentor engineers; define best practices

Qualification

· 4–8 years of hands-on DFT experience with ownership of block/SoC-level DFT implementation

· Able to independently drive DFT tasks from insertion to sign-off with minimal supervision

· Strong expertise in scan (stitching/compression), ATPG, DFT DRC, MBIST (with repair),

LBIST basics, JTAG/Boundary Scan (IEEE 1149.1), and low-power DFT

· Good debugging skills across DFT insertion, ATPG patterns, and coverage closure

· Proficient in Cadence / Siemens (Mentor) DFT tool flows

· Strong scripting skills (Tcl/Perl/Python) for automation and debug

· Solid understanding of RTL, Lint/CDC, low-power intent, and ASIC design flow

· Able to collaborate effectively with RTL, PD, and STA teams to close DFT and coverage issues

Soft Skills

· Ability to independently drive coverage closure and DFT signoff for complex SoCs

· Structured debugging approach across RTL, ATPG, scan/BIST, and silicon failures

· Explicit communication of coverage metrics, risks, and silicon readiness status

· Capability to mentor engineers and lead technical design reviews

· Strong ownership mindset and execution discipline

· Ability to manage multiple deliverables under tight timelines

📌 DFT ENGINNER (Bengaluru)
🏢 Brace Infotech Private
📍 Bengaluru