**Design Verification Engineer

About the Opportunity

We are hiring Design Verification Engineers for our client, a leading product and service-based technology company. The opportunity is for professionals who are passionate about semiconductor and VLSI technologies and want to work on challenging design and verification projects.**

? **Immediate Joiners PreferredCandidate s who can join immediately or within a short notice period are strongly preferred.

Role & R e sponsibilities

- Develo p and execute verification plans for complex digital designs. Create and maintain testbenches, test cases, and verification environments. Develop verification components using SystemVerilog and UVM. Perform functional, block-level, and system-level verification. Analyze simulation results and debug design/verification issues. Work cl osely with RTL design, architecture, and other engineering teams. Identif y, track, and close functional and code coverage gaps. Perform regression testing and analyze failures. Contrib ute to improving verification methodologies and processes.* Partici pate in design reviews, verification reviews, and project discussions.

Required

Skills

- Strong knowledge of Digital Electronics and VLSI concepts. Hands-o n experience with SystemVerilog. Valuable un derstanding of UVM methodology.



Experie nce in developing and debugging verification environments. Knowled ge of functional coverage, code coverage, assertions, and constrained-random verification. Experie nce with simulation and debugging tools. Good un derstanding of RTL and digital design concepts.* Strong analytical and problem-solving skills.

Preferre d

Skills

- Experi e nce with AMBA protocols such as AXI, AHB, or APB. Knowled ge of SVA (SystemVerilog Assertions). Experie nce with simulators such as VCS, Questa, or Xcelium. Exposur e to scripting languages such as Python, Perl, or TCL. Experie nce working on SoC, IP, ASIC, or semiconductor projects.

Experien c e

4+ years of relevant experience in Design Verification.

Locat~~ion

? **Bangalore | Chennai | Kochi | Pune

Employmen t Type

Full-tim e

How to A p ply

Interest e d candidates can share their updated resume with the subject line “Design Verification Engineer – Immediate Joiner” at:

? **[email protected]

Please me ntion your current location, total experience, relevant experience, and notice period while applying.

VS Techn o logies is the hiring partner for this opportunity. The selected candidates will be employed by our client organization.

📌 Design Verification Engineer (Bengaluru)
🏢 VS Technologies
📍 Bengaluru