Develop and execute comprehensive IP-level verification plans based on design specifications.

Develop reusable and scalable SystemVerilog/UVM-based verification environments.

Create test scenarios, test cases, sequences, and functional coverage models.

Develop and maintain UVM components including agents, drivers, monitors, sequencers, scoreboards, and reference models.

Write SystemVerilog assertions (SVA) for protocol and functional verification.

Perform simulation, regression testing, coverage analysis, and functional debugging.

Analyze simulation failures and work closely with RTL designers to identify and resolve issues.

Achieve and track functional and code coverage targets.

Verify standard protocols such as AXI, AHB, APB, PCIe, USB, I2C, SPI, or other relevant interfaces.

Develop verification collateral that can be reused across projects and IP variants.

Participate in design reviews, verification reviews, and coverage closure activities.

Support formal verification and/or emulation activities when required.

Document verification results, bugs, coverage status, and sign-off criteria.





Required Skills Strong knowledge of Digital Design and Verification concepts.

Hands-on experience with SystemVerilog.

Strong understanding of UVM methodology.

Experience developing UVM testbenches and verification components.

Good knowledge of functional coverage, code coverage, assertions, and constrained-random verification.

Experience with simulation/debug tools such as VCS, Questa/ModelSim, Xcelium, or equivalent.

Valuable understanding of RTL design and common SoC/IP protocols.

Strong debugging and problem-solving skills.

Familiarity with Linux/Unix environments and scripting.

Good to Have

Experience with Formal Verification.

Knowledge of Python, Perl, Shell, or Tcl scripting.

Experience with CDC/RDC verification.

Experience with AMBA protocols, PCIe, DDR, Ethernet, USB, or other high-speed interfaces.

Familiarity with CI/CD-based verification regressions.

Experience with coverage closure and IP-level sign-off.

📌 Design Verification Engineer (IP Level) (Kolkata Metropolitan Area)
🏢 People Prime Worldwide
📍 Kolkata Metropolitan Area