Role:

Design Verification Engineer

Location:

Bangalore

Experience:

6+ years

Notice:

upto 15 days

Mandatory Technical Expertise:

Candidates should have solid, hands-on experience in the following areas:

- Digital / SoC Verification with 6+ years of relevant experience

- Strong expertise in SystemVerilog (SV) and UVM

- Hands-on experience with PCIe and/or UCIe protocols

- Strong understanding of SoC architecture and verification methodologies

- Good programming skills in C / C++

- Test Case Development – ability to develop comprehensive and reusable verification test cases

- Test Plan Development – experience in defining verification strategies, test plans, coverage goals, and execution

- Strong debugging and failure-analysis skills

- Experience in identifying, reproducing, analyzing, and resolving complex verification issues

- Good understanding of functional verification, coverage, regression, and verification closure

📌 Design Verification Engineer (Bangalore Metropolitan Area)
🏢 HappieHire
📍 Bangalore Metropolitan Area